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1997 data sheet mos integrated circuit m pd72001-11, 72001-a8 multi-protocol serial controllers document no. s12184ej7v0ds00 (7th edition) date published november 1997 n printed in japan description the m pd72001-11 is an mpsc (multi-protocol serial controller) which is a general-purpose communication lsi equipped with two sets of bidirectional parallel/serial converter circuits for data communication. this controller has a transmitter function to convert the parallel data output by a data terminal into serial data and transmit this data to a data transmission system such as a modem, and a receiver function to convert the serial data output by the data transmission system into parallel data. the mpsc can be used with data communications equipment with a variety of communication modes such as the generally and widely used start-stop synchronization mode, and the hdlc mode which is used for high-speed communication. the m pd72001-a8 is a low-voltage model. for this product, the following documents are separately available. read these documents as well as this data sheet. ? users manual (s12472e) (i) (s12753e) ? application notes (ii) (on preparation) (iii) (on preparation) features ? two sets of parallel/serial circuits supporting three modes: start-stop synchronization, character synchronization, and bit synchronization modes ? easy application to a system supporting two or more communication protocols such as a protocol converter or isdn terminal adapter ? dpll (digital phase locked loop), baud rate generator, and crystal oscillation circuit for transmission/reception clock ? helps reduce cost by decreasing the number of external circuits ? many variations with power-saving features and small package size ? easy application to portable terminals and high-accuracy portable terminals the features common to the m pd72001-11 and 72001-a8 are explained as the features of the mpsc in this document. y t the information in this document is subject to change without notice. the mark shows major revised points.
m pd72001-11, 72001-a8 2 ordering information part number package m pd72001c-11 40-pin plastic dip (600 mil) m pd72001g-11-22 44-pin plastic qfp (10 10 mm) (resin thickness: 1.45 mm) m pd72001gc-11-3b6 52-pin plastic qfp (14 14 mm) (resin thickness: 2.7 mm) m pd72001l-11 52-pin plastic qfj (750 750 mil) m pd72001c-a8 40-pin plastic dip (600 mil) m pd72001g-a8-22 44-pin plastic qfp (10 10 mm) (resin thickness: 1.45 mm) m pd72001gc-a8-3b6 52-pin plastic qfp (14 14 mm) (resin thickness: 2.7 mm)
m pd72001-11, 72001-a8 3 specifications item specifications part number m pd72001-11 m pd72001-a8 supply voltage 5 v 10 % 3.3 v 0.3 v system clock frequency 11 mhz max. 8 mhz max. (at t a = C10 to +70 c) 7.14 mhz max. (at t a = C40 to +85 c) maximum transfer rate 2.2 mbps 1.6 mbps (at t a = C10 to +70 c) 1.43 mbps (at t a = C40 to +85 c) process cmos internal circuit parallel/serial converter circuit: full-duplex channel 2 transmit buffer : double receive buffer : quadruple interrupt control function dma request signal output: 2 for transmission, 2 for reception overrun error detection dpll baud rate generator crystal oscillation circuit for transmission/reception clock generation self-loopback test function standby function general-purpose i/o pin: 4 pins 2 communication protocol start-stop character bit length: 5, 6, 7, 8 synchronization stop bit length: 1, 1.5, 2 clock rate: 1, 16, 32, 64 parity generation, check framing error detection break generation, detection cop operation mode: mono-sync, bi-sync, external sync (character character bit length: 5, 6, 7, 8 oriented sync character bit length: 6, 8 protocol) character synchronization: internal/external bcs (block check sequence) generation, check: crc-16 crc-ccitt parity generation, check sync character automatic transmission, detection, rejection bop operation mode: (bit oriented hdlc (high-level data link control) protocol) sdlc (synchronous data link control) sdlc loop flag transmission, detection zero insertion, rejection address field detection (1 byte) fcs (frame check sequence) generation, detection short frame detection abort automatic transmission, detection idle detection go ahead detection transmit number data control processing data format encode/decode of nrz (non-return to zero) encode/decode of nrzi (non-return to zero inverted) encode/decode of fm (frequency modulation) decode in manchester mode
m pd72001-11, 72001-a8 4 pin configuration (top view) ? 40-pin plastic dip (600 mil) : m pd72001c-11, m pd72001c-a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 dcda d7 d6 d5 d4 d3 d2 d1 d0 gnd wr rd c/d b/a pro pri intak int ctsb dcdb 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ctsa r x da xi1a/str x ca xi2a/synca tr x ca t x da rtsa drqr x a reset clk v dd drqt x a dtra/drqt x b dtrb/drqr x b rtsb t x db xi2b/syncb xi1b/str x cb r x db tr x cb ? 44-pin plastic qfp (10 10 mm) : m pd72001g-11-22, m pd72001g-a8-22 1 2 3 4 5 6 7 8 9 10 11 rtsb dtrb/drqr x b dtra/drqt x b drqt x a v dd v dd clk reset drqr x a rtsa t x da 33 32 31 30 29 28 27 26 25 24 23 pro b/a c/d rd wr gnd gnd d0 d1 d2 d3 tr x ca xi2a/synca xi1a/str x ca r x da ctsa ic dcda d7 d6 d5 d4 t x db xi2b/syncb xi1b/str x cb r x db tr x cb ic dcdb ctsb int intak pri 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 ic: internally connected (leave this pin unconnected)
m pd72001-11, 72001-a8 5 ? 52-pin plastic qfp (14 14 mm) : m pd72001gc-11-3b6, m pd72001gc-a8-3b6 1 2 3 4 5 6 7 8 9 10 11 12 13 t x da tr x ca xi2a/synca xi1a/str x ca r x ca ctsa ic dcda d7 d6 d5 d4 d3 39 38 37 36 35 34 33 32 31 30 29 28 27 rtsb t x db xi2b/syncb xi1b/str x cb r x db tr x cb ic dcdb ctsb int intak pri pro nc d2 nc d1 d0 gnd gnd wr rd c/d b/a nc nc nc nc rtsa drqr x a reset clk v dd v dd drqt x a dtra/drqt x b dtrb/drqr x b nc nc 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 nc: no connection ic : internally connected (leave this pin unconnected.) ? 52-pin plastic qfj (750 750 mil) : m pd72001l-11 8 9 10 11 12 13 14 15 16 17 18 19 20 d2 nc d1 nc d0 gnd gnd wr rd c/d nc b/a nc 46 45 44 43 42 41 40 39 38 37 36 35 34 nc rtsa drqr x a nc reset clk v dd v dd drqt x a dtra/drqt x b nc dtrb/drqr x b nc pro pri intak int ctsb dcdb nc tr x cb r x db xi1b/str x cb xi2b/syncb t x db rtsb d3 d4 d5 d6 d7 dcda nc ctsa r x da xi1a/str x ca xi2a/synca tr x ca t x da 7654321525150494847 21 22 23 24 25 26 27 28 29 30 31 32 33
m pd72001-11, 72001-a8 6 block diagram dtra/drqt x b t x buf. cr 6-7 transmitter r x buf. sr0 4-7 0-3 sr1-4 10-11 receiver t x r x cont. cr/sr 8-9 brg -h,l brg sr 12-15 dpll t x r x clk cont. osc t x r x clk cr 0-5 10-15 cont. sign. ch.b t x db r x db ctsb dcdb xi2b/syncb xi1b/str x cb tr x cb rtsb db buf. rd/wr cont. dma cont. rd wr c/d reset b/a drqr x a drqt x a dtrb/drqr x b pro int cont. int intak pri d7-0 clk/stby cont. system clk clk interface cont. tr x ca xi1a/str x ca xi2a/synca dcda ctsa r x da t x da rtsa r x clk t x clk internal bus ch.a
m pd72001-11, 72001-a8 7 1. pin functions the functions of the mpsc can be broadly classified into system interface functions that control interfacing with the host system, and transmission/reception functions to transmit or receive data. this section explains the functions of the pins of the mpsc by classifying the pins into those related to system interfacing and those related to transmission and reception. hereafter, h (voltage level satisfying v ih in the case of an input pin, or voltage level satisfying v oh in the case of an output pin) and l (voltage level satisfying v il in the case of an input pin, or voltage level satisfying v ol in the case of an output pin) are used to indicate the input/output status of a pin. 1.1 pins related to system interface (1) v dd supply voltage pin (2) gnd gnd pin (3) reset ... input this pin inputs a signal from an external device to reset the mpsc. when l is input to this pin for the duration of 2 clock cycles (2t cyk ) or longer, the mpsc is reset (this is called system reset). as a result of system reset, the transmitter, receiver, and interrupt/dma functions of the mpsc are disabled, and the t x d pin and general-purpose output pins go high. in this case, because all bits of the control register (cr) are also reset, cr must be set again if a system reset has been executed. table 1-1 shows the status of each pin at system reset, in comparison with the pin status at channel reset (cr0: d5, d4, d3 = 0, 1, 1). the mpsc automatically enters the standby mode at system reset, lowering the power consumption from that in the normal operation mode.
m pd72001-11, 72001-a8 8 table 1-1. pin status at reset pin name i/o pin status reset (system reset) channel reset wr i C C rd i C C b/a i C C c/d i C C d7 to d0 i/o C C int o high impedance high impedance intak i C C pri i C C pro o depends on pri depends on pri drqt x a o l l drqr x a o l l dtra/drqt x b, o dtr function, h retains current status dtrb/drqr x b t x da, t x db o h h r x da, r x db i C C tr x ca, tr x cb i/o input status retains current status xi1a/str x ca i C C xi1b/str x cb xi2a/synca i/o input status retains current status xi2b/syncb rtsa, rtsb o h h ctsa, ctsb i C C dcda, dcdb i C C C : undefined (4) clk (system clock) ... input this pin inputs the system clock. the input frequency must be five times that of the data transfer rate or higher. (5) wr (write) ... input this pin inputs a write control signal for control words and transmit data. this pin is active-low. (6) rd (read) ... input this pin inputs a read control signal for status and receive data. this pin is active-low. (7) b/a (channel b/channel a) ... input this pin inputs a signal to select a channel to be accessed when data is written or read. when this pin is l, channel a is selected; when it is h, channel b is selected. (8) c/d (control/data) ... input this pin inputs a signal that determines the type of the data on the data bus when the data is written or read.
m pd72001-11, 72001-a8 9 table 1-2 shows the selection operations by wr, rd, b/a, and c/d. table 1-2. mpsc control signals and operations wr rd b/a c/d operation l h l l channel a writes transmit data to t x buffer h channel b h l l l channel a reads receive data from r x buffer h channel b l h l h channel a writes control register h channel b h l l h channel a reads status register h channel b hh high-impedance state or intak sequence ll setting prohibited : dons care (9) d7 through d0 (data bus) ... i/o these pins constitute a three-state 8-bit bidirectional data bus. this data bus is connected to the data bus of the host processor to transfer control words, status, and transmit/receive data. (10) int (interrupt) ... output (open drain) this pin outputs an interrupt request signal. if an interrupt occurs in the mpsc, it goes low (active). because this is an open-drain output pin, it must be pulled up. (11) intak (interrupt acknowledge) ... input this pin inputs a signal to acknowledge interrupt request signals issued by the mpsc. this pin is active-low. this pin is used when the vector mode (cr2a: d7 = 1) is selected, and must be pulled up to h when the non- vector mode (cr2a: d7 = 0) is selected. (12) pri (priority input) ... input this input pin is used for an interrupt generation request signal and for an output control signal for interrupt vectors. in the normal operation mode, this pin provides an interrupt generation control function. during the intak sequence, it provides an output control function for interrupt vectors. how this pin is used differs depending on the interrupt mode. (a) in vector mode (cr2a: d7 = 1) in the normal operation mode, the pri pin is used to control generation of interrupts. when interrupt vector output mode of type a-3 or type b-2 (cr2a: d5, d4, d3 = 0, 1, 0 or 1, 0, 0) is selected, interrupts can be generated regardless of whether the pri pin is l or h. if any other interrupt vector output mode is selected, the pri pin must be kept l to enable generation of interrupts. during the intak sequence, an interrupt vector is output if l is input to the pri pin in any interrupt vector output mode, and output of the interrupt vector is disabled if h is input to pri.
m pd72001-11, 72001-a8 10 (b) non-vector mode (cr2a: d7 = 0) in this mode, the pri pin controls only the generation of interrupts because the intak sequence is not used. if an interrupt vector output mode other than type a-3 and type b-2 is selected, generation of an interrupt signal is enabled if l is input to the pri pin. the interrupt signal is not generated if h is input to pri. if an interrupt daisy chain is configured, inputting l to this pin indicates that a device having a higher priority does not acknowledge interrupt processing or does not have an interrupt request, and only the mpsc with l input to its pri pin can generate an interrupt. (13) pro (priority output) ... output this pin is used when an interrupt daisy chain is configured. this output pin is active-low, and controls generation of interrupts requests from a device with a lower priority. usually, this pin is used along with the pri pin, and its operation is as follows: when pri = h, pro = h when pri = l, pro goes h if there is an interrupt request, and goes l if there is no interrupt request. (14) drqt x a (dma request t x a) ... output this pin outputs a dma request to a dma controller. this pin is active-high. it goes h if the transmitter of channel a has entered the t x buffer empty status. the condition under which this pin goes h differs as follows depending on the setting of the cr1 and d2 bits. cr1: d2 = 0: the drqt x a pin goes h when the transmitter has entered the t x buffer empty status after the first transmit data has been written. it does not go h when the transmitter has entered the t x buffer empty status after reset. cr1: d2 = 1: the drqt x a pin goes h when the transmitter has entered the t x buffer empty status. this signal is reset when transmit data has been written to channel a. (15) drqr x a (dma request r x a) ... output this pin outputs a dma request to a dma controller. this pin is active-high and goes h if the receiver of channel a has entered the r x character available status. this signal is reset only when receive data has been read from channel a. (16) dtra/drqt x b (data terminal ready a/dma request t x b) ... output the function of this pin is changed as follows depending on the setting of cr2a: d1 and d0. (a) when cr2a: d1, d0 = 0, 0 or 0, 1 this pin functions as the dtra pin. this pin is a general-purpose output pin and can be used to control a modem, etc. the operation of the dtra pin is as follows: when cr5a: d7 = 0, dtra = h when cr5a: d7 = 1, dtra = l (b) when cr2a: d1, d0 = 1, 0 this pin functions as the drqt x b output pin. the function of this pin is the same as the drqt x a pin, except this pin is used with channel b. (17) dtrb/drqr x b (data terminal ready b/dma request r x b) ... output the function of this pin changes as follows depending on the setting of cr2a: d1 and d0.
m pd72001-11, 72001-a8 11 (a) when cr2a: d1, d0 = 0, 0 or 0, 1 this pin functions as the dtrb output pin. the function of this pin is the same as the dtra pin, except this pin is used with channel b. (b) when cr2a: d1, d0 = 1, 0 this pin functions as the drqr x b output pin. the function of this pin is the same as the drqrxa pin, except this pin is used with channel b. (18) ctsa (clear to send a) and ctsb (clear to send b) ... input this pin is a general-purpose input pin and can be used to control a modem, etc. changes in the status of this pin affect the latching operation of the e/s bit. when e/s int is enabled (cr1: d0 = 1), the e/s interrupt is generated. if the auto enable mode (cr3: d5 = 1) is set, the transmitter can be controlled by using the t x enable bit (cr5: d3) and this pin. this is illustrated in table 1-3. table 1-3. auto enable mode and cts pin cts pin t x enable bit transmitter status l 1 enabled h 1 disabled h or l 0 disabled (19) dcda (data carrier detect a) ... input dcdb (data carrier detect b) ... input these are general-purpose input pins and can be used to control a modem, etc. changes in the status of this pin affect the latching operation of the e/s bit. when e/s int is enabled (cr1: d0 = 1), the e/s interrupt is generated. if the auto enable mode (cr3: d5 = 1) is set, the receiver can be controlled by using the r x enable bit (cr3: d0) and this pin. this is illustrated in table 1-4. table 1-4. auto enable mode and dcd pin dcd pin r x enable bit receiver status l 1 enabled h 1 disabled h or l 0 disabled (20) rtsa (request to send a) ... output rtsb (request to send b) ... output these are general-purpose output pins and can be used to control a modem, etc. the operations of these pins differ depending on the setting of the operation protocol and the setting of the auto enable bit, as shown in table 1-5.
m pd72001-11, 72001-a8 12 table 1-5. auto enable bit and rts pin function protocol auto enable bit rts cont. bit rts pin status start-stop 0 0 h synchronization 1l 1 when 0 from beginning h if set to 1 once and then reset if l while all sent note = 0, to 0 and h if all sent = 1 1l cop/bop dont care 0 h 1l note sr1: d2 1.2 pins related to transmission/reception (1) t x da (transmit data a) and t x db (transmit data b) ... output these pins output transmit data. (2) rxda (receive data a) and rxdb (receive data b) ... input these pins input receive data. (3) xi1a/str x ca (crystal input 1a/source of transmit receive clock a) ... input xi1b/str x cb (crystal input 1b/source of transmit receive clock b) ... input the functions of these pins change depending on the setting of cr15: d7. (a) when cr15: d7 = 0 these pins function as the str x c pins, and input the transmission and reception clocks, or input source clocks to the internal brg (baud rate generator) and dpll (digital phase locked loop). (b) when cr15: d7 = 1 these pins function as xi1 pins and connect one end of the crystal for transmission/reception clock source oscillation. (4) xi2a/synca (crystal input 2a/synchronization a) ... i/o xi2b/syncb (crystal input 2b/synchronization b) ... i/o the functions of these pins change depending on the setting of cr15: d7. (a) when cr15: d7 = 0 these pins function as sync pins. the functions of the sync pins differ as shown in table 1-6, depending on the setting of cr4. (b) when cr15: d7 = 1 these pins function as xi2 pins and connect one end of the crystal for transmission/reception clock source oscillation.
m pd72001-11, 72001-a8 13 table 1-6. functions of sync pins and setting of cr4 (when cr15: d7 = 0) operation synchronization sync pin cr4 protocol detection mode function d7 d6 d5 d4 d3 d2 function start-stop input 0 1 the sync pins function as general-purpose synchro- 1 0 input pins. changes in the status of these pin nization 1 1 (h ? l or l ? h) affect the latch operation of the sync/hunt bit (sr1: d4), and cause the e/s interrupt. cop internal output 00 if a sync character is detected in the receive synchro- character, the sync pins go l for the nization 01 duration of 1r x c cycle. external input 0 0 1 1 0 0 the sync pins input a signal for establishing synchro- character synchronization. when these pins nization go l from h, execution exits from the hunt phase and character synchronization is established. while sync input is l, 0 1 character synchronization is maintained. assembling a receive character is started at the rising edge of the receive clock preceding the falling of the sync input. bop no function 1 0 the sync pins do not function. : dont care caution if a pattern in which 1 bit (0 or 1) is inserted in between the sync character assigned to cr7 and sync character assigned to cr6 is received while data is being assembled in the bi-sync mode, an l pulse of about 1 bit may be generated on the sync pin. if the enter hunt command is issued while this l pulse is present, the command is invalid. however, the recieve operation of the mpsc is not affected at all by the reception of this pattern. (5) tr x ca (transmit receive clock a) ... i/o tr x cb (transmit receive clock b) ... i/o (a) when cr15: d2 = 0 these pins input the transmit and receive clocks. they are used to supply external transmit and receive clocks. [exception] if either cr15: d6, d5 = 0, 1 or d4, d3 = 0, 1, or both are set, the tr x ca and tr x cb pins function as input pins, even if cr15: d2 = 1. (b) when cr15: d2 = 1 these pins function as output pins. the source of the output clock can be selected from a crystal oscillation circuit, brg, dpll, or transmit clock, depending on the setting of cr15: d1, d0. under the conditions explained in [exception] in (a) above, they unconditionally serve as input pins, and the setting of cr15: d2, d1, d0 is invalid.
m pd72001-11, 72001-a8 14 2. system configuration example an example of a system where the m pd72001-11 is used for a terminal adapter for isdn is shown below. rs-232-c d/r pd72002-11 m hdlc sync async cpu (with dmac) pd72001-11 m hdlc sync async hdlc sync async pd98201 m s-i/f dch bch trans- former rom ram terminal adapter for isdn isdn circuit personal computer bus
m pd72001-11, 72001-a8 15 3. electrical specifications (1) m pd72001-11 absolute maximum ratings (t a = 25 c) parameter symbol condition ratings unit supply voltage v dd C0.5 to +7.0 v input voltage v i C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v operating temperature t a C40 to +85 c storage temperature t stg C65 to +150 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. dc characteristics m pd72001-11 (t a = C40 to +85 c, v dd = 5 v 10 %) parameter symbol condition min. typ. max. unit high-level input voltage v ihc clk, str x c, tr x c 3.3 v dd + 0.5 v v ih other pins 2.2 v dd + 0.5 v low-level input voltage v ilc clk, str x c, tr x c C0.5 +0.6 v v il other pins C0.5 +0.8 v high-level output voltage v oh i oh = C400 m a 0.7 v dd v low-level output voltage v ol i ol = 2.0 ma 0.45 v high-level input leakage current i lih v i = v dd 10 m a low-level input leakage current i lil v i = 0 v C10 m a high-level output leakage current i loh v o = v dd 10 m a low-level output leakage current i lol v o = 0 v C10 m a supply current i dd at 11 mhz 20 40 ma in standby mode note 1ma note system clock : 11 mhz input pin : inactive ? high-level input voltage : (v dd C 0.3 v) to (v dd + 0.5 v) ? low-level input voltage : 0 v to 0.3 v output pin : leave unconnected.
m pd72001-11, 72001-a8 16 capacitance (t a = 25 c, v dd = 0 v) parameter symbol condition min. max. unit input capacitance c in f c = 1 mhz 10 pf i/o capacitance c io pins other than test pin: 0 v 20 pf ac characteristics m pd72001-11 (t a = C40 to +85 c, v dd = 5 v 10 %) system interface: parameter symbol condition rated value unit min. max. clock cycle t cyk 90 2 000 ns clock high-pulse width t wkh 40 1 000 ns clock low-pulse width t wkl 40 1 000 ns clock rise time t kr 1.5 v ? 3.0 v 10 ns clock fall time t kf 3.0 v ? 1.5 v 10 ns address setup time (vs. rd )t sar 0ns address hold time (vs. rd - )t hra 0ns rd pulse width t wrl 120 ns address ? data output delay time t dad t a = C10 to +70 c 100 ns t a = C40 to +85 c 110 rd ? data output delay time t drd t a = C10 to +70 c 100 ns t a = C40 to +85 c 110 rd ? data float delay time t frd 10 85 ns address setup time (vs. wr )t saw 0ns address hold time (vs. wr - )t hwa 0ns wr pulse width t wwl 120 ns data setup time (vs. wr - )t sdw t a = C10 to +70 c 100 ns t a = C40 to +85 c90 data hold time (vs. wr - )t hwa 0ns recovery time between rd and wr t rv 140 ns
m pd72001-11, 72001-a8 17 serial control: parameter symbol condition rated value unit min. max. transmit/receive data cycle t cyd 5t cyk str x c, tr x c input clock cycle t cyc 90 ns str x c, tr x c input high t wch 40 ns clock pulse width low t wcl t a = C10 to +70 c40ns t a = C40 to +85 c45 str x c, tr x c ? t x d delay time t dtctd1 1 mode, cop, bop 100 ns t dtctd2 16, 32, 64 mode 300 ns tr x c ? t x d delay time t dtctd3 tr x c is output 0 100 ns r x d setup time (vs. str x c, tr x c - )t srdrc when dpll is not used 0 ns r x d hold time (vs. str x c, tr x c - )t hrcrd when dpll is not used 120 ns r x d ? t x d delay time t drdtd1 echo back mode 100 ns t drdtd2 without sdlc loop delay 100 ns t x d ? int delay time t dtdiq t x int mode 4 6 t cyk t x d ? drqt x delay time t dtddq t x dma mode 4 6 t cyk r x c - note ? int delay time t drciq r x int mode 7 11 t cyk r x c - note ? drqr x delay time t drcdq r x dma mode 7 11 t cyk rd ? drqr x delay time t drdq 120 ns wr ? drqt x delay time t dwdq 120 ns note of str x c and tr x c, the one used as the receive clock. interrupt control: parameter symbol condition rated value unit min. max. intak low-pulse width t wial 120 ns intak high-pulse width t wiah 120 ns pri ? pro delay time t dpipo 50 ns int ? pro - delay time t diqpo C20 +50 ns 2nd intak ? int - delay time t diaiq int output level = 0.8 v note 120 ns int output level = 2.2 v note 300 ns sr2b read rd ? int - delay time t drdiq int output level = 0.8 v note 150 ns int output level = 2.2 v note 300 ns pri setup time (vs. intak )t spiia1 when vector output is enabled 0 ns pri hold time (vs. intak - )t hiapi1 20 ns pri setup time (vs. intak )t spiia2 when vector output is disabled 20 ns pri hold time (vs. intak - )t hiapi2 20 ns intak ? data output delay time t diad 120 ns intak ? data float delay time t fiad 10 85 ns note measured value with 2-k w pull-up resistor and 100-pf load capacitance connected
m pd72001-11, 72001-a8 18 modem control: parameter symbol condition rated value unit min. max. cts, dcd, sync pulse high t wmh 2t cyk width low t wml 2t cyk cts, dcd, sync ? int delay time t dmiq 2t cyk str x c, tr x c - ? sync setup time t ssyrc cop external synchronization 0 2 t cyk communication control: parameter symbol condition rated value unit min. max. transmit enable command t dtetd1 async, cop 3 t cyc (wr - , cts ) ? t x d delay time t dtetd2 bop 4 7 t cyc receive enable command (dcd )t srerc 1t cyc setup time (vs. start bit, str x c - , tr x c - of sync character) note receive enable command (dcd )t hrcre1 async 7 t cyk hold time (vs. str x c - , tr x c - ) note t hrcre2 cop 20t cyc + 8t cyk t hrcre3 bop 3t cyc + 8t cyk receive clock (str x c, tr x c) note t hrdrc1 async 1 bit hold time (vs. stop bit, msb of crc, t hrdrc2 cop 22 t cyc msb of end flag) t hrdrc3 bop 5 t cyc receive clock (str x c, tr x c) note t srcrd1 async 1 bit setup time (vs. start bit, sync character) t srcrd2 cop, bop 1 t cyc note of str x c and tr x c, the one used as the receive clock. crystal oscillation and reset parameter symbol condition rated value unit min. max. xi1 input cycle time t cyx 90 2000 ns reset pulse width t wrsl 2t cyk caution the system clock cycle in all modes must be five times that of the data rate.
m pd72001-11, 72001-a8 19 ac test input/output waveform (except clock) 2.2 0.8 2.2 0.8 test points 2.4 0.45 ac test clock input waveform 3.3 0.6 3.3 0.6 test points load condition dut c l = 100 pf c l includes jig capacitance caution if the load capacitance exceeds 100 pf due to the configuration of the circuit, keep the load capacitance of this device to within 100 pf by inserting a buffer or by some other means. remark dut: tested device
m pd72001-11, 72001-a8 20 (2) m pd72001-a8 absolute maximum ratings (t a = 25 c) parameter symbol condition ratings unit supply voltage v dd C0.5 to +7.0 v input voltage v i C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v operating temperature t a C40 to +85 c storage temperature t stg C0 to +150 c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. dc characteristics (t a = C40 to +85 c, v dd = 3.3 v 0.3 v) parameter symbol condition min. typ. max. unit high-level input voltage v ihc clk, str x c, tr x c 0.8 v dd v dd + 0.5 v v ih other pins 1.8 v dd + 0.5 v low-level input voltage v ilc clk, str x c, tr x c C0.5 0.15 v dd v v il other pins C0.5 +0.6 v high-level output voltage v oh i oh = C400 m a 2.2 v low-level output voltage v ol i ol = 2.0 ma 0.5 v high-level input leakage current i lih v i = v dd 10 m a low-level input leakage current i lil v i = 0 v C10 m a high-level output leakage i loh v o = v dd 10 m a current low-level output leakage i lol v o = 0 v C10 m a current supply current i dd at 8 mhz 5 20 ma in standby mode note 1ma note system clock : 8 mhz (t a = C10 to +70 c)/7.14 mhz (t a = C40 to +85 c) input pin : inactive ? high-level input voltage : (v dd C 0.3 v) to (v dd + 0.5 v) ? low-level input voltage : 0 v to 0.3 v output pin : leave unconnected. capacitance (t a = 25 c, v dd = 0 v) parameter symbol condition min. max. unit input capacitance c in f c = 1 mhz 10 pf i/o capacitance c io pins other than test pin: 0 v 20 pf
m pd72001-11, 72001-a8 21 ac characteristics (t a = C40 to +85 c, v dd = 3.3 v 0.3 v) system interface: parameter symbol condition rated value unit min. max. clock cycle t cyk t a = C10 to +70 c 125 2000 ns t a = C40 to +85 c 140 2000 ns clock high-pulse width t wkh 50 1000 ns clock low-pulse width t wkl 50 1000 ns clock rise time t kr 1.5 v ? 2.2 v 10 ns clock fall time t kf 2.2 v ? 1.5 v 10 ns address setup time (vs. rd )t sar t a = C10 to +70 c0ns t a = C40 to +85 c5 address hold time (vs. rd - )t hra t a = C10 to +70 c0ns t a = C40 to +85 c5 rd pulse width t wrl t a = C10 to +70 c 150 ns t a = C40 to +85 c 155 address ? data output delay time t dad t a = C10 to +70 c 120 ns t a = C40 to +85 c 125 rd ? data output delay time t drd t a = C10 to +70 c 120 ns t a = C40 to +85 c 125 rd ? data float delay time t frd 10 120 ns address setup time (vs. wr )t saw 0ns address hold time (vs. wr - )t hwa t a = C10 to +70 c0ns t a = C40 to +85 c5 wr pulse width t wwl t a = C10 to +70 c 150 ns t a = C40 to +85 c 155 data setup time (vs. wr - )t sdw t a = C10 to +70 c 120 ns t a = C40 to +85 c 125 data hold time (vs. wr - )t hwd t a = C10 to +70 c0ns t a = C40 to +85 c5 recovery time between rd and wr t rv t a = C10 to +70 c 180 ns t a = C40 to +85 c 190
m pd72001-11, 72001-a8 22 serial control: parameter symbol condition rated value unit min. max. transmit/receive data cycle t cyd 5t cyk str x c, tr x c input clock cycle t cyc t a = C10 to +70 c 125 dc ns t a = C40 to +85 c 140 dc ns str x c, tr x c input t wch high level t a = C10 to +70 c50dcns clock pulse width t a = C40 to +85 c55dcns t wcl low level t a = C10 to +70 c60dcns t a = C40 to +85 c65dcns str x c, tr x c ? delay time t dtctd1 1 mode, cop, t a = C10 to +70 c 140 ns bop t a = C40 to +85 c 145 ns t dtctd2 16, 32, 64 mode t a = C10 to +70 c 300 ns t a = C40 to +85 c 305 ns tr x c ? txd delay time t dtctd3 tr x c is output 0 100 ns r x d setup time (vs. str x c, tr x c - )t srdrc when dpll is t a = C10 to +70 c0 ns not used t a = C40 to +85 c5 ns r x d hold time (vs. str x c, tr x c - )t hrcrd when dpll is t a = C10 to +70 c 140 ns not used t a = C40 to +85 c 145 ns r x d ? t x d delay time t drdtd1 echo back mode 100 ns t drdtd2 without sdlc loop delay 100 ns t x d ? int delay time t dtdiq t x int mode 4 6 t cyk t x d ? drqt x delay time t dtddq t x dma mode 4 6 t cyk rxc - note ? int delay time t drciq r x int mode 7 11 t cyk rxc - note ? drqr x delay time t drcdq r x dma mode 7 11 t cyk rd ? drqr x delay time t drdq 140 ns wr ? drqt x delay time t dwdq 140 ns note of str x c and tr x c, the one used as the receive clock.
m pd72001-11, 72001-a8 23 interrupt control: parameter symbol condition rated value unit min. max. intak low-pulse width t wial 150 ns intak high-pulse width t wiah 150 ns pri ? pro delay time t dpipo 50 ns int ? pro - delay time t diqpo C20 +50 ns 2nd intak ? int - delay time t diaiq int output level = 0.8 v note 120 ns int output level = 1.8 v note 300 ns sr2b read rd ? int - delay time t drdiq int output level t a = C10 to +70 c 170 ns = 0.8 v note t a = C40 to +85 c 180 ns int output level = 1.8 v note 350 ns pri setup time (vs. intak )t spiia1 when vector output is enabled 0 ns pri hold time (vs. intak - )t hiapi1 20 ns pri setup time (vs. intak )t spiia2 when vector output 20 ns pri hold time (vs. intak - )t hiapi2 is disabled t a = C10 to +70 c20 ns t a = C40 to +85 c25 ns intak ? data output delay time t diad 120 ns intak ? data float delay time t fiad 10 130 ns note measured value with 2-k w pull-up resistor and 100-pf load capacitance connected modem control: parameter symbol condition rated value unit min. max. cts, dcd, sync high t wmh 2t cyk pulse width low t wml 2t cyk cts, dcd, sync ? int delay time t dmiq 2t cyk str x c, tr x c - ? sync setup time t ssyrc cop external synchronization 0 2 t cyk
m pd72001-11, 72001-a8 24 communication control: parameter symbol condition rated value unit min. max. transmit enable command (wr - ,t dtetd1 async, cop 3 t cyc cts ) ? t x d delay time t dtetd2 bop 4 7 t cyc receive enable command (dcd )t srerc 1t cyc setup time (vs. start bit, str x c - , tr x c - of sync character) note receive enable command (dcd )t hrcre1 async 7 t cyk hold time (vs. str x c - , tr x c - ) note t hrcre2 cop 20 t cyc + 8t cyk t hrcre3 bop 3t cyc + 8t cyk receive clock (str x c, tr x c) note t hrdrc1 async 1 bit hold time (vs. start bit, msb of crc, t hrdrc2 cop 22 t cyc msb of end flag) t hrdrc3 bop 5 t cyc receive clock (str x c, tr x c) note t srcrd1 async 1 bit setup time (vs. start bit, sync character) t srcrd2 cop, bop 1 t cyc note of str x c and tr x c, the one used as the receive clock. crystal oscillation and reset: parameter symbol condition rated value unit min. max. xi1 input cycle time t cyx t a = C10 to +70 c 125 1000 ns t a = C40 to +85 c 140 1000 reset pulse width t wrsl 2t cyk caution the system clock cycle in all modes must be five times that of the data rate.
m pd72001-11, 72001-a8 25 ac test input waveform (except clock) 1.8 0.6 1.8 0.6 test points 2.2 0.5 ac test clock input waveform 0.8 v dd 0.15 v dd 0.8 v dd 0.15 v dd test points load condition dut c l = 100 pf c l includes jig capacitance caution if the load capacitance exceeds 100 pf due to the configuration of the circuit, keep the load capacitance of this device to within 100 pf by inserting a buffer or by any other means. remark dut: tested device
m pd72001-11, 72001-a8 26 clock timing clk t cyk t wkl t wkh t kf t kr read cycle timing c/d, b/a rd t sar t wrl t hra d7-0 t drd t frd t dad hi-z hi-z write cycle timing c/d, b/a wr t saw t wwl t hwa d7-0 t hwd hi-z hi-z t sdw read/write cycle timing (except transfer of transmit/receive data) rd, wr t rv
m pd72001-11, 72001-a8 27 transmit cycle timing str x ca/b tr x ca/b t x da/b int drqt x a/b t cyc t wcl t wch t dtctd3 t cyd t dtdiq t dtddq receive cycle timing str x ca/b tr x ca/b r x da/b int drqr x a/b t cyc t wcl t wch t srdrc t hrcrd t drciq t drcdq t cyd
m pd72001-11, 72001-a8 28 transmitter enable timing cts wr t x d t dtetd1 , t dtetd2 receiver enable timing str x c tr x c r x d note dcd t srerc note lsb of the first receive data (sync, flag) receive clock setting timing a. in async mode str x c tr x c r x d t srcrd1 start bit b. in cop/bop mode str x c tr x c r x d note t srcrd2 note lsb of sync pattern (sync, flag)
m pd72001-11, 72001-a8 29 dcd timing, receive clock hold timing a. in async mode str x c tr x c r x d stop bit dcd t dcy 2 1 t hrdrc1 t hrcre1 b. cop/bop mode str x c tr x c r x d note dcd t hrcre2 , t hrcre3 t hrdrc2 , t hrdrc3 note this bit is the msb of bcs in the cop mode and msb of the end flag in the bop mode. in echo back mode and loop mode r x d t x d t drdtd1 , t drdtd2
m pd72001-11, 72001-a8 30 dma cycle timing drqt x a/b drqr x a/b rd t drdq wr t dwdq pro output timing pri int pro t dpipo t diqpo intak cycle timing intak pri (when vector output is enabled) pri (when vector output is disabled) rd d7-0 int t spiia2 t hiapi2 t spiia1 t wiah t hiapi1 t wial t diad t fiad hi-z hi-z t diaiq t drdiq
m pd72001-11, 72001-a8 31 e/s timing ctsa/b, dcda/b, synca/b int t wml t wmh t dmiq sync input timing (external synchronization mode) synca/b note t ssyrc str x ca/b tr x ca/b last bit of sync character 1st bit of data character note synca/b input must be cleared to 0 at the rising edge of r x c two clock cycles after the last bit of the sync character. xi1 input timing xi1 t cyx reset pulse reset t wrsl
m pd72001-11, 72001-a8 32 4. package 40pin plastic dip (600 mil) item millimeters inches notes 1) each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. n 0.25 0.01 a 53.34 max. 2.100 max. b 2.54 max. 0.100 max. f 1.2 min. 0.047 min. g 3.6?.3 0.142?.012 j 5.72 max. 0.226 max. k 15.24 (t.p.) 0.600 (t.p.) c 2.54 (t.p.) 0.100 (t.p.) d 0.50?.10 0.020 +0.004 ?.005 h 0.51 min. 0.020 min. i 4.31 max. 0.170 max. l 13.2 0.520 m 0.25 0.010 +0.004 ?.003 +0.10 ?.05 m i h g f dn c b p40c-100-600a-1 r 0~15 0~15 2) ltem "k" to center of leads when formed parallel. 120 40 21 a j r m k l
m pd72001-11, 72001-a8 33 44 pin plastic qfp ( 10) b a 33 23 34 22 111 44 12 c d f g h j i m p k l n detail of lead end s 5?5? q m note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p44g-80-22-2 item millimeters inches a b c d f g h i j k l m n p q s 13.6 0.4 0.15 1.65 max. 10.0 0.2 10.0 0.2 13.6 0.4 1.0 1.0 0.2 +0.10 ?.05 1.45 0.1 0.05 0.05 0.15 0.8 (t.p.) 1.0 0.35 0.10 1.8 0.2 0.15 0.039 0.039 0.535 +0.017 ?.016 0.394 +0.008 ?.009 0.394 +0.008 ?.009 0.535 +0.017 ?.016 0.006 0.031 (t.p.) 0.014 +0.004 ?.005 0.071 +0.008 ?.009 0.039 +0.009 ?.008 0.006 +0.004 ?.003 0.006 0.002 0.002 0.065 max. 0.057 +0.005 ?.004
m pd72001-11, 72001-a8 34 n m k l p i j h g c d b a f 39 40 52 1 26 27 14 13 q 55 s detail of lead end p52gc-100-3b6,3bh-2 item millimeters inches note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (t.p.) 1.8 0.2 0.8 0.2 0.15 0.10 2.7 0.1 0.1 3.0 max. 0.693 0.016 0.551 0.551 0.693 0.016 0.039 0.039 0.016 0.008 0.039 (t.p.) 0.071 0.031 0.006 0.004 0.106 0.004 0.004 0.119 max. a b c d f g h i j k l m n p q s +0.10 ?.05 +0.004 ?.003 +0.009 ?.008 +0.008 ?.009 +0.004 ?.005 +0.009 ?.008 +0.009 ?.008 52 pin plastic qfp ( 14) m
m pd72001-11, 72001-a8 35 52 pin plastic qfj ( 750 mil) a 52 b 1 c d f e u n t q m m k i g h j p p52l-50a1-2 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. +0.007 ?.006 a b c d e f g h i j k m n p q t u 20.1 0.2 19.12 19.12 20.1 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 min. 3.4 1.27 (t.p.) 0.40 0.10 0.12 18.04 0.20 0.15 r 0.8 0.20 0.791 0.753 0.753 0.791 0.076 0.024 0.173 0.110 0.035 min. 0.134 0.050 (t.p.) 0.016 0.005 0.710 0.006 r 0.031 0.008 +0.009 ?.008 +0.009 ?.008 +0.10 ?.05 +0.004 ?.002 +0.009 ?.008 +0.009 ?.008 +0.009 ?.008 +0.004 ?.005
m pd72001-11, 72001-a8 36 5. recommended soldering conditions it is recommended to solder this product under the following conditions. for details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. surface mount type ? m pd72001g-11-22 : 44-pin plastic qfp (10 10 mm) m pd72001g-a8-22 : 44-pin plastic qfp (10 10 mm) soldering method soldering condition recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (210 c min.), number of times: 2 max., number of days: 7 note (after that, prebaking for 10 hours at 125 c is necessary.) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (200 c min.), number of times: 2 max., number of days: 7 note (after that, prebaking for 10 hours at 125 c is necessary.) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-107-1 number of times: 1, preheating temperature: 120 c max. (package surface temperature), number of days: 7 note (after that, prebaking for 10 hours at 125 c is necessary.) products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) note the number of days the product can be stored at 25 c, 65 % rh max. after the dry pack has been opened. caution do not use two or more soldering methods in combination (except partial heating).
m pd72001-11, 72001-a8 37 ? m pd72001gc-11-3b6 : 52-pin plastic qfp (14 14 mm) m pd72001gc-a8-3b6: 52-pin plastic qfp (14 14 mm) soldering method soldering condition recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (210 c min.), number of times: 3 max. vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (200 c min.), number of times: 3 max. wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 number of times: 1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) caution do not use two or more soldering methods in combination (except partial heating). ? m pd72001l-11: 52-pin plastic qfj (750 750 mil) soldering method soldering condition recommended condition symbol vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-1 (200 c min.), number of times: 1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) through-hole type ? m pd72001c-11 : 40-pin plastic dip (600 mil) m pd72001c-a8: 40-pin plastic dip (600 mil) soldering method soldering condition wave soldering (pins only) solder bath temperature: 260 c max., time: 10 seconds max. partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin) caution when soldering this product using of wave soldering, exercise care that the solder does not come in direct contact with the package.
m pd72001-11, 72001-a8 38 [memo]
m pd72001-11, 72001-a8 39 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd72001-11, 72001-a8 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed : m pd72001-a8 license needed : m pd72001-11

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